Iterated Systems needed very fast turnaround (4 days) for this one-shot design of an ASIC emulator to keep their chip development schedule on track.

..our single instruction was.. “go”

..knowing that this design had to fly through the fab house, with no testing, we optimized the placement for autorouting using “anybody can build it” design rules, and still needed only 6 layers. This is where our “system” had to work, flawlessly. Everything from footprint retrieval, proven design rule sets, workhorse CAD tools, and over 20 years of experience putting it all together.

In developing products for the highly competitive PC market, American Megatrends looks closely at reducing manufacturing costs through stringent design rules, layer reduction, via minimization, panelization, and generation of N.C. drive data for automated component assembly and board test.

And don't make any mistakes.

A common design cycle at American Megatrends involves creating and debugging a board design in-house and then submitting the design to us for the production layout. In the volumes of their production runs, the re-layout costs can provide a pay-back in a matter of months. In addition to PC adapter cards, we have designed over 20 motherboards for AMI.

Even large companies can experience a bottle-neck in board layout. System level products often involve many board layouts hitting the pipeline in a short period of time, taxing even the best equipped design groups. A side-effect is that the “less important” details of supporting documentation get postponed in favor of getting the designs on the engineers bench, sometimes creating havoc (and expense) down the line in production.

We have made special efforts to provide a complete documentation package as part of our design services. We can generate publication quality schematic, drill, fabrication and assembly drawings and deliver within one day of generating the tooling set and getting the board into production.

Many RF design engineers are skeptical of placing their layouts in someone else's hands, much less a service bureaus'. In trying several service bureaus, SPC Electronics found out the hard way that the feeling was mutual.

Accomodating a customers' design methods and priorities is the most important ingredient of a good design service. In this 2.575 GHZ design, individual microstrip geometries were mathematically generated by the engineers' simulation software which we built as discrete components. The rest of the layout was prioritized by highlighting the critical signal path on the schematic, with each stage approved through check plots. Most importantly, the “final analysis” involved direct side-by-side input from the engineer at our workstation.

A real frankenstein: mixed surface mount and through-hole components, mixed analog and digital circuitry; split/partial power and ground planes; over 1100 components, very high density... and the dreaded A-to-D converters!

A problem with this design was the interface between the analog and digital circuitry. A large number to analog signals tied into the digital section at various points, and vice versa; board I/O requirements would not allow placement to solve this problem. Compounding the problem was an engineering request that all analog signals be accessible for, er.. possible modification. The analog/digital interaction was minimized by partitioning the signals crossing the placement boundary onto their own layer pairs, creating a 3 dimensional partition. The analog signals were restricted to the two outer layers, with the analog power and ground planes occupying the 4 internal layers. The digital section was routed on the full 4 signal layers, with 2 internal power planes.

With 300+ externally generated clocks and high speed data signals required in this graphics hardware, and a lot of real estate to cover, many of these signals ended up running the full length of the board. BAD BAD BAD!

The component density was approaching ground zero, so their simply weren't ANY routing channels to accomodate shielded clocks. Rather than surrounding these signals with discrete “ground guard” traces, they were embedded within 6 dedicated ground plane layers, alternating between other signal layers. This provided excellent shielding between layers as well as between clocks on the same layer. The routing was further partitioned into six routing “slopes”, since traditional orthogonal routing would have choked on vias. The design was accomplished with only 114 vias.

Many engineering firms focusing on developing state-of-the-art products simply do not have the tools, time, or personnel to support their own demanding PCB development schedules. They may go for months wearing their “R&D” hats, then switch to production mode for several months getting product to customers. With this kind of cyclical development schedule, it's hard to justify the investment needed to maintain the thru-put we can provide (at the drop of a hat). They have enough challenges on their hands.

Aside from providing top quality layout services, we can provide everything a full-blown drafting and procurement department would. Depending on the fabrication technology required, we coordinate with a number of board vendors during the final days of layout so the minute the layout is approved, it can be transmitted to the vendor of choice. The same day, Gray Labs can begin incorporating our publication quality schematic diagrams, assembly drawings, and parts lists into their customer documentation package. We also electronically exchange data with their mechanical designers to verify form and fit.